In meantime i found i can use following syntax: sync : entity work.sync2 generic map ( n => 2 ) port map ( d(0) => sig1, q(0) => sig2, reset => reset, clk => clk ); 0 Kudos Copy link Reply Community support is provided Monday to Friday. Other contact met...
I declare the entity doing the operations as a component in the file with the carry look ahead adder. However, when I compile I get the following error: Error (10500): VHDL syntax error at <location> near text ";"; expecting ":=", or "<=" Error (1050...
Yes, but what if n = 1. How do I code it? In meantime i found i can use following syntax: sync : entity work.sync2 generic map ( n => 2 ) port map ( d(0) => sig1, q(0) => sig2, reset => reset, clk => clk ); Translate 0 Kudos Copy link Reply Comm...
simp_cpu port map ( start => pl_go, mic_in => err, kd => kd, ki => ki, kp => kp, z_out => u, done => go, clk => clk_op ); U_dtdk_plant: dtdk_plant port map( x_in => x_in, u_in => u, go => go, clk => clk, clk_op => clk_op, err => err, ...
Error (10500): VHDL syntax error at data_subsys.vhd(21) near text ":="; expecting ";" Thank you very much. Translate 0 Kudos Copy link Reply Altera_Forum Honored Contributor II 01-12-2011 05:42 PM 3,712 Views You cannot initialise a type, you have to initialise a cons...
simp_cpu port map ( start => pl_go, mic_in => err, kd => kd, ki => ki, kp => kp, z_out => u, done => go, clk => clk_op ); U_dtdk_plant: dtdk_plant port map( x_in => x_in, u_in => u, go => go, clk => clk, clk_op => clk_op, err => err, ...