这里主要是看designer主要关注什么指标,如果是关注dutycycle,那么选择Edge Delay比较合适。 Sampled Phase:采样的相位分析。Sampled phase是可以用来测量固定时刻点的jitter,Samples Per Period是用来指定每周期测量多少个时刻点,Initial Sample Phase是用来指定第一个Sample的时刻。Add Specific Points用来指定特别关注的时刻点...
Sampled Phase：采样的相位分析。Sampled phase是可以用来测量固定时刻点的jitter，Samples Per Period是用来指定每周期测量多少个时刻点，Initial Sample Phase是用来指定第一个Sample的时刻。Add Specific Points用来指定特别关注的时刻点。大家可以看到，Noise Type后面有个Sample Ratio选项，什么意思呢？该选项主要用在有...
Noise type设置为sampled(jitter)。这种方法会计算pss过程中某一时刻的采样噪声。这个时刻由下面设置的event type决定。 Event type=edge crossing, Trigger=voltage, Output Nodes=/outp and /outn(这两个是comparator的输出node,注意这个必须是cross-coupled transistor的输出),Edge number=1, Threshold value=0.05(...
select the fullspectrum method for sidebands and choose 'sampled(jitter)' as the noise type.Event type is crucial here. Set it to 'edge crossing' with Trigger set to 'voltage', using nodes /outp and /outn (cross-coupled transistor outputs). The threshold value should be 0.05...
noisetype=sampled measurement=[pm0] annotate=status pm0 jitterevent trigger=[DUT.LATCH\<5\>.vOUTp \ DUT.LATCH\<5\>.vOUTm] triggerthresh=(PNOISE__vREGENd) \ triggernum=1 triggerdir=rise target=[DUT.LATCH\<5\>.vOUTp \ DUT.LATCH\<5\>.vOUTm] ...
So every 24 period, I replace the zero crossing of the unjected signal with the zero crossing of a clean reference to lower the jitter. In this case I have a reference with frequency of 100MHz. (I need to inject that "not clean" signal, because it creats a topology that gives a ...