It leverages the recent introduction of additional real number capabilities in System Verilog to represent analog signals, known by Real Number Modeling (RNM). In addition to the introduction of composite user-defined net types that can carry multiple information, e.g. voltage, current, impedance,...
In particular, because period jitter is measured across a single period, the bandwidth within which the period can be modified is very limited, so the real probability will be lower than calculated. The designer of a system must choose the acceptable probability of jitter being above the peak ...
In this work, a digital phase-locked loop real number model using SystemVerilog is presented, in order to greatly improve simulation efficiency while keeping accuracy in a satisfying level. The proposed digital PLL real number model consists of a phase frequency detector (PFD), a charge pump, ...