I can not seem to find the Makefile which should be modified to solve this issue. How do I solve this issue? Expand Post LikeReply UA (Member) 2 years ago Does your design have any custom IP? If yes, you can f...
17:21:38INFO:lopper command to generate BSP:python3/tools/Xilinx/vitis2023/Vitis/2023.1/data/embeddedsw-sdt/scripts/rigel_scripts//create_bsp.py -w /home/nnguyen/IRAD_GIT/IRAD-Vivado-DDR-Streaming/Vitis-app/zcu208_platform2023/zynqmp_fsbl/zynqmp_fsbl_bsp ...