25 changes: 23 additions & 2 deletions 25 drivers/net/phy/marvell.c Original file line numberDiff line numberDiff line change @@ -214,6 +214,11 @@ #define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7) #define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)...
4. 依赖资源 chip_phy6220 drv_bt_phy6220 5. 开发板烧录 5.1. 烧录工具 PHY6220烧录工具PhyPlusKit下载,支持通过串口烧录镜像。 打开烧写工具PhyPlusKit.exe 勾选UART Setting,选择开发板串口,串口配置为波特率:115200,停止位:1,校验:NO 点击Connect,连接串口 选择Flash_writer标签页 选择HEX烧入方式标签页 双击...
In STM32CubeIDE 1.8.0, I was able to configure a custom PHY without any issues. Could you please provide guidance on how to set up and configure a custom PHY in version 1.14.1? Any information on handling this in the latest versions to avoid warnings and allow ...
Add CONFIG_PREBOOT to provide an automatic and easier way to configure ethernet PHY before loading the firmware. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-19-kishon@ti.co...
I have installed the SW32R45_TCPIP_STACK_1_0_1_D2202, and import lwip_s32r45 project. According to the description of the project, it can connect to PC and ping. But i can't find the code to initialize or configure phy in lwip demo. Why is there no code f...
Part Number:PROCESSOR-SDK-DRA7X Hi, At present, in the mass production stage, some hardware will be completely disconnected from the Internet. We want to clarify whether it is a MAC problem or a PHY problem. The manufacturer (RTK) of the device PHY has...
Using Quartus Pro 18.1, FPGA number is 10AX027H2F35E1HG. Trying to configure a Transceiver Native Phy to 12.75G link rate. I have the PCS mode set
The Cisco Smart PHY application requires SSH to log in directly to the exec mode on the Cisco cBR-8 router. When a device is added or updated using this profile, the content you specify here is applied to the device.Step 4 Click Save. Apply...
Hi, i am trying to configure the external phy from CPU via MDIO slave but i am able to read even address in phy registers but not able to read odd address registers from phy. Subscribe More actions DheeraJ Beginner 10-01-2019 07:42 AM 1,440...
The DS90UH940N-Q1 provides internal register control, which enables end users to configure their desired D-PHY timing.Davor Glisic