PIPE 是适用于 PCI Express, SATA, 以及 USB 等总线架构的物理层协议,全称 The PHY Interface for the PCI Express, SATA, and USB Architectures (以下简称 PIPE) 。 译注:从 PIPE 的缩写看来看出,本协议原本仅为 PCIe 开发。 PIPE 协议设计初衷在于使开发兼容 PCIe,USB 以及 SATA 等总线的多功能 PHY 成为...
PHY Interface For the PCI Express, SATA, and USB 3.1 Architectures Version 4.3 ©2007 - 2014 Intel Corporation—All rights reserved. 3 PHY/MAC interface 图3-1 展示了 PHY 和 MAC 层模块之间的数据以及逻辑命令/状态信号。本文档的第 5 节将会讨论这些信号。支持 PCI Express, SATA, 以及 USB ...
PHY Interface For the PCI Express, SATA, USB 3.1, DisplayPort, and Converged IO Architectures Version 5.1 ©2007 - 2018 Intel Corporation—All rights reserved. PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and Converged IO Architectures, ver 5.1 Intellectu...
PHY Interface for the PCI Express* Architecture Intellectual Property Disclaimer THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR ...
Rambus PCIe 2.1 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controller is compliant with the PCI Express 2.1 specification, as well as with the PHY Interface for ...
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and chip-to-chip channels. The PHY’s unique DSP algorithms optimize receiver equalization and the patent-pending diagnostics features enable near ...
PHY Interface for the PCI Express Architecture Version 2.0 PHY Interface for the PCI Express Architecture Version 2.0 上传者:da895时间:2011-01-20 ddr_for_controller_and_phy_ddrphy_ddr_chargeone_fpgaphy_ddr_cont 这是本人曾经参与的一个DDR controller接口项目,主要是FPGA rtl实现,仅供参考。
The invention discloses an elastic buffer circuit of PIPE (PHY Interface For the PCI Express*and USB 3.0 Architectures). The elastic buffer circuit comprises a command word generating circuit, a command word buffer, a data buffer, a command word analysis circuit and an output data controller, ...
[7]徐君明,裴先登,王海卫等,高性能计算机 1/0 技术 PCIExpress 分析,计算机工 程,2004,30(12):6～7,151 TechnicalAnalysisofPHYInterfaceforPCIExpressBus LRuiMeiHanXiaoYi 1.HebeiInstituteofArchitectureandCivilEngineering 2.ZhangjiakouHongzeDrainageCo.Ltd AbstractInthispaper,weanalysethearchitectureandthe...
Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully...