Proposed is a phase-frequency detector, PFD, circuit suitable for use in a phase lock loop, PLL, circuit. The PFD circuit comprises: a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase...
A sequential phase-frequency detector circuit using precharged logic and a minimum number of transistors is suitable for use in a delay locked loop because of insensitivity to a stuck delay line output signal. The detector receives standard REFERENCE and LOCAL input signals and provides UP and ...
The present invention provides a cycle slip detector circuit for use with a phase and frequency detector circuit having first and second signal inputs, and arranged to provide first and second PLL control signal outputs responsive to clock edges in the first and second input signals respectively; ...
The pull-in range,\pm \Delta \omega_P, is defined as the range of input frequencies that the DPLL will lock to. If the center frequency of the DPLL is 10 MHz and the pull-in range is 1 MHz, the DPLL will lock on an input frequency from 9 to 11 MHz in a time TP (assuming N...
A fast locking phase-locked loops (PLL) with a dual-slope phase frequency detector circuit is presented. 文中提出了一种用于高速锁相环的双斜鉴频鉴相器的结构设计。 www.dictall.com 5. of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks. 相位频率检测器(PFD)和修改其他...
which is configured to receive the respective other part of the high-frequency signals which have been split, and a complementary filter device ( 50 ) which is configured to receive the output signals from the self-calibrating phase detector module ( 30 ) and the low-noise phase detector modul...
A lock-in enhanced phase-locked loop with high speed phase frequency detector In this paper, we first systematically analyze existing phase frequency detectors from aspects of theoretical analysis and circuit operation. Based on the ... HC Chow,NL Yeh 被引量: 27发表: 2005年 A Phase Frequency ...
专利名称:Phase frequency detector 发明人:Thomas P. Thomas 申请号:US08/820154 申请日:19970319 公开号:US05963058A 公开日:19991005 摘要:Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a phase frequency detector (PFD) including two clock input ports, an ...
This article provides an overview of frequency generation methods and explains why a translation loop device is the best choice.
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