Just for my understanding, if I were to drive pin BB17 PCIE_RT_S10_PERSTn constant High, would the Max10 then only assert the PERST to EP Pin if the above condition is fulfilled, i.e. main power is stable? @hareesh wrote:[...] and can be based on the PER...
For the Pcie refclk, I will be in SRNS that seems supported by Pcie IP. How to deal with perstn ? I'am used to work with common refclk and persnt, but unfortunatelly these signal not passed through the active cable (SFF-8644). For sure I can generate a nrst signal for example whe...
The name of the Signal is PCIE_RT_S10_PERSTn. The Pin is not mentioned in the Stratix 10 User-Guide. What's the purpose of the Pin, and how do we need to use it in a Design using a PCI Express Hard IP-Core configured as Root-Port? Perstn is a PCIe res...
I am only aware of a Perst input to the RP IP-Core itself, which isn't driven by user logic but connects to PIN B10 S10_PCIE_PERSTn1. Kind regards! 翻訳 0 件の賞賛 リンクをコピー 返信 hareesh 従業員 09-27-2023 04:35 AM 2,184件の閲覧回数 Hi,...