如上图所示:所有的根总线都链接在pci_root_buses链表中. Pci_bus ->device链表链接着该总线下的所有设备.而pci_bus->children链表链接着它的下层总线. 对于pci_dev来说,pci_dev->bus指向它所属的pci_bus. Pci_dev->bus_list链接在它所属bus的device链表上.此外,所有pci设备都链接在pci_device链表中. 三:...
if (pci_find_bus(pci_domain_nr(b), bus)) { /* If we already got to this bus through a different bridge, ignore it */ pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); goto err_out; } //--创建总线加入PCI总线链表 down_write(&pci_bus_sem); list_add...
struct pci_bus *bus; /* bus this device is on 设备所在的bus*/ struct pci_bus *subordinate; /* bus this device bridges to 当作为PCI桥设备时,指向下级bus */ void *sysdata; /* hook for sys-specific extension */ struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ ...
pci_find_next_bus(判断是否扫描过)->pci_scan_bus_parented(扫描pci父总线) pci_create_bus( 创建总线对象,添加到pci_root_buese链表,以及建立资源管理对象Ioport、Iomem) pci_scan_child_bus(扫描子总线)->pci_scan_bridge(根据设备的类型进一次扫面,对桥的扫面)-> pci_read_config_dword(读取pci配置空间...
while ((bus = pci_find_next_bus(bus)) != NULL) { if (bus->number == busnum) { /* Already scanned */ return bus; } } /* Allocate per-root-bus (not per bus) arch-specific data. * TODO: leak; this memory is never freed. ...
Bus Master:控制pci设备是否具有作为Master角色的权限。 status字段用来记录pci设备的状态信息,virtio-blk是(0x10 = 0x10000),status各字段含义如下图: 其中有一位是Capabilities List,它是pci规范定义的附加空间标志位,Capabilities List的意义是允许在pci设备配置空间之后加上额外的寄存器,这些寄存器由Capability List组...
static int find_free_domain(void) { int domain = 0xffff; struct pci_bus *bus = NULL;while ((bus = pci_find_next_bus(bus)) != NULL) domain = max_t(int, domain, pci_domain_nr(bus));return domain + 1; }static int find_remapped_devices(struct nvme_remap_dev *nrdev, ...
UBOOT 的PCI 扫描 pci_init_board()是进行pci 扫描的起始函数,这个函数中会用到几个重要的结构体: struct pci_controller { struct pci_controller *next; int first_busno; int last_busno; volatile unsigned int *cfg_addr; volatile unsigned char *cfg_data; struct pci_region regions[MAX_PCI_REGIONS...
DEVICE_BUS_SPECIFIC_RESET_TYPE union DEVICE_CAPABILITIES structure DEVICE_DESCRIPTION structure DEVICE_DIRECTORY_TYPE enumeration DEVICE_FAULT_CONFIGURATION structure DEVICE_INSTALL_STATE enumeration DEVICE_INTERFACE_CHANGE_NOTIFICATION structure DEVICE_OBJECT structure DEVICE_POWER_STATE enumeration DEVICE_QUERY_BUS...
3.6 PCIe Reset – Cold Reset: PCI A15 pin RST – Warm Reset (LTSSM) – Hot Reset (LTSSM): PCIe Type1 Header config space offset 0x3E 16-bit Bridge Control register bit6 Secondary Bus Reset, bit6 can retrigger LTSSM Link Training from Rx.Detect – FLR (Function Level Reset): find Syn...