noearly: 在内核启动过程的开始阶段,禁用对PCI设备的早期扫描(使用type1方式尝试访问每个可能存在的PCI设备的配置空间)。 assign-busses: 内核将无视PCI BIOS分配的总线号,自己重新分配;枚举包括总线号分配和其他地址空间的分配。此处仅指总线号重新分配。 routeirq: 内核为PCI设备分配中断路由。PCI驱动可能漏调用pci_...
在pci_create_bus()中,为对应总线号构建pci_bus,然后将其挂入到pci_root_buses链表.该函数代码比较简单,请自行分析.然后,调用然后pci_scan_child_bus枚举该总线下的所有设备.pci_bus->subordinate表示下流总线的最大总线号.pci_sacn_child_bus()代码如下: unsigned int __devinit pci_scan_child_bus(struct p...
pci_bus 0001:c3: busn_res: can not insert [bus c3-c2] under [bus c2] (conflicts with (null) [bus c2])--失败 pci_bus 0001:c3: scanning bus pci_bus 0001:c3: fixups for bus pci_bus 0001:c3: bus scan returning with max=c3 pci_bus 0001:c3: busn_res: [bus c3-c2] end is u...
28#definePCI_ASSIGN_ALL_BUSSES0x4000 PCI_PROBE_BIOS对应了BIOS方式,PCI_PROBE_MMCONF对应了MMConfig方式,这好理解,看名字就知道了,不好理解的是PCI_PROBE_CONF1和PCI_PROBE_CONF2都对应了Direct方式,这是因为曾经有过两种PCI Configuration Mechanism,用行话来说就是Type1和Type2,内核要想不通过BIOS直接去访问...
* fallback, yet it's needed to run first to set pcibios_last_bus * in case legacy PCI probing is used. otherwise detecting peer busses * fails. */ #ifdef CONFIG_PCI_DIRECT pci_direct_init(type); #endif if (!raw_pci_ops)
* fallback, yet it's needed to run first to set pcibios_last_bus * in case legacy PCI probing is used. otherwise detecting peer busses * fails. */ #ifdef CONFIG_PCI_DIRECT pci_direct_init(type); #endif if (!raw_pci_ops)
pcibios_assign_all_busses() ? " " : " (try 'pci=assign-busses')"); printk(KERN_WARNING "Please report the result to " "<bk@suse.de> to fix this permanently\n"); pr_debug("PCI: Bus #%02x (-#%02x) is %s" "hidden behind%s bridge #%02x (-#%02x)\n", child->number, child...
...//总线已经被bios设置好了if((buses &0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {if(pass)//第二次gotoout; ...//已经存在if(pci_find_bus(pci_domain_nr(bus), busnr)) {gotoout; }//不存在分配一个新总线child =pci_add_new_bus(bus, dev, busnr); ...//...
分别为所有PCI总线和设备,分配pci_bus和pci_dev管理对象,记录设备信息(比如,将映射的内存和I/O区间,记录到resource成员,将连接的中断控制器请求线,记录到irq成员)。 2. “配置寄存器组”头部 “配置寄存器组”,一方面提供设备的出厂信息,另一方面,用于系统软件对设备进行配置。其中,前64字节,必须按照PCI标准...
IP Compiler for PCI Express User Guide August 2014 Altera Corporation Chapter 4: IP Core Architecture Application Interfaces 4–3 The PCI Express Avalon-ST adapter maps PCI Express transaction layer packets (TLPs) to the user application RX and TX busses. Figure 4–2 illustrates this interface....