Horan D M,Guinee R.A novel pulse echo correlation tool for transmission path testing and fault finding using pseudorandom binary sequences. IEEE International Symposium on Defect and Fault Tolerance in VLSI Sys-
if the measured slack associated with one or more of the flip-flops106-109is found by the decision module115to be less than a predetermined minimum value, then the decision module115causes the regulator controller116to adjust Vdd in order to improve performance, as a reduced slack margin may ...
Synchronous or pipelined memories often use clock signals for timing certain functions associated with the memory core. Incorrectly designed, manufactured, or margined time settings in these clock signals may cause failures to be observed at output register 106 even though the memory core itself is ...
The novel training and retraining algorithm trains each PI for its corresponding data eye eliminating the need for any duty cycle correction of the PI output while maximizing the eye margin.Chowdhury, NasirulWight, JeffMozak, ChrisKurd, Nasser...
Figure 1. Example of ranking changes in timing paths after aging. In order to mitigate the NBTI effect on timing closure, circuit designers generally set targeted timing margins at the early design phase to cover harsh timing scenarios after aging. Then, finding an optimal margin is significant...
Synchronous or pipelined memories often use clock signals for timing certain functions associated with the memory core. Incorrectly designed, manufactured, or margined time settings in these clock signals may cause failures to be observed at output register 106 even though the memory core itself is ...