0.1 Full Adder 首先考虑对于1比特的输入加法:如图所示,FA 的输入有三个:,,和。其中,和代表输入,表示低位的进位。输出中,表示本位置的结果,表示对高位的进位。其真值表和逻辑门表示如下。 下图中,half adder表示对于两输入的加法电路求和,而右图则表示FA具体利用AND、 XOR...
本文将对并行前缀加法器（Parallel Prefix Adder, PPA）进行深入探讨，以优化布尔状态下2-输入加法的效率，并在安全多方计算中的算术分享与布尔分享转化中发挥作用。首先，我们从全加器（Full Adder, FA）入手，介绍其构建方法与优化。全加器用于处理1比特的加法，其输入包括两个数和低位进位，输出为本位...
Disclosed is a parallel prefix adder structure with a carry bit generation circuit that generates primary carry bits for only some bit pairs and a sum circuit with ripple carry adders that use these primary carry bits to generate secondary carry bits and sum bits for a final sum. The carry ...
Number of parallel prefix adder structures have been proposed over the past years intended to optimize area, fan-out, logic depth and inter connect count. This paper investigates the performance of different parallel prefix adders when they are implemented on an FPGA. The comparison has been done...
The present work focused on designing of high performance low power 8-bit parallel prefix adder structure. For improving the speed and to reduce the power, we have reduced the static power and dynamic power. The design is simulated using Xilinx 13.2 ISE and implemented on Spartan 3 FPGA Board...
Parallel prefix adder is a general technique for speeding up binary addition. In unit delay model, we denote the size and depth of an n-bit prefix adder C(n) as SC(n) and dC(n) respectively. Snir proved that sC(n) + dC(n) ≥ 2n - 2 holds for arbitrary prefix adders. Hen...
Experimental results indicate that the proposed adder has an improvement of 21 percent time delay and 25 percent area compared to the traditional Ling adders.关键词: VLSI design parallel-prefix algorithm Ling adder logic optimization DOI: 10.1109/ICECC.2011.6066361 被引量: 3 ...
We propose a low-overhead fault-secure parallel prefix adder. We duplicate carry bits for checking purposes. Only one half of normal carry bits are compared with the corresponding redundant carry bits, and the hardware overhead of the adder is low. For concurrent error detection, we also predi...
A Novel Modulo$2^{n}-2^{k}-1$Adder for Residue Number System Modular adder is one of the key components for the application of residue number system (RNS). Moduli set with the form of 2(n) - 2(k) - 1 (1 <= k <= n -2)... S Ma,JH Hu,CH Wang - 《IEEE Transactions on...
Efficient modulo $2^n+1$ adder architectures. Summary: We introduce novel carry lookahead (CLA) and parallel-prefix architectures for the design of modulo $2^n+1$ adders with operands in the diminished... HT Vergos,C Efstathiou - 《Integration the Vlsi Journal》 被引量: 68发表: 2009年 ...