Therefore, a parallel adder can be adapted to provide the2’s complementof a number, allowing it to function as both an adder and a subtractor. This design usesXOR gates, as shown in Figure 1. Here M-line acts as a control line i.e. depending on the value provided at M, the circuit...
In a carry-select type adder/subtractor as another embodiment, if split parallel process is to be executed, both a pair of unit adders/subtractors execute an arithmetic operation to be carried out for the case where no carry is supplied from lower digits, and then a selector selects an ...
Parallel Adder/Subtractor using a single circuit can be also designed using a Mod bit (M), where mod bit M decides whether the circuit will act as an adder or a subtractor. When M=0, then the circuit acts as an adder and when M=1, then the circuit acts as a subtractor. The ...
[511:0] result; reg reset; //Testbench specific variables integer i; parameter CLK_PERIOD = 10; adder_subtractor uut( .dataa(input1), .datab(input2), .add_sub(add_sub), .clk(clk), .result(result), .reset(reset), .select(select) ); initial begin clk = 1'b0; add_sub = 0;...
Based on this realization of ternary full-adder we propose realization of a ternary parallel adder with partially-look-ahead carry. We also show the method of using the same circuit as a ternary parallel adder/subtractor. 展开 关键词: Logic synthesis Quantum circuit Ternary logic ...
A NOVEL DESIGN OF REVERSIBLE SERIAL AND PARALLEL ADDER/SUBTRACTOR Under ideal conditions, Reversible logic gates produce zero power dissipation. So these can be used for low power VLSI design. This paper proposes a new re... D Krishnaveni.,PM Geetha - 《International Journal of Engineering Scien...
8421 carry-lookahead adder tree8421-5421 BCD multiplierPPAPPGTSMC technologyParallel decimal multiplications can be broadly divided into two major steps: ... Z Ming,AM Baker,Y Jiang - IEEE 被引量: 0发表: 2013年 Serial tetrad adder/subtractor mechanism in BCD 8421 code The subject-matter of th...
In addition, we propose a quaternary quantum reversible parallel adder/subtractor circuit. The proposed designs are compared with existing designs and improvements in terms of hardware complexity, quantum cost, number of constant inputs and garbage outputs are reported. 展开 ...
adder subtractor 加法器,加减法器 adder accumulator 【计】 加法累加器 adder subtracter 【计】 加减器 adder's mouth n. [植]沼兰属植物 subtracted adder 加法-减法器 最新单词 Chenopodium ambrosioides L.的中文意思 【医】 土荆芥 Chenopodium album Linn.什么意思及同义词 【医】 藜 chenopodium...
关键词: Hybrid SET-CMOS MIB BSIM4.6.1 Single Electron Transistor 4-bit parallel adder/subtractor circuit 会议名称: 2014 17th International Conference on Computer and Information Technology, ICCIT 2014 会议时间: 02 April 2015 主办单位: IEEE