A VLSI synthesis tool for complementary output delta modulation FIR filtersdoi:10.1016/0165-6074(92)90120-VAn application specific high level synthesis tool is presented for designing linear Delta Modulation (DM) FIR filters, with parallel implementation of their complementary responses, using a Kaiser...
Matsuura, "Realization of multiple-output functions by reconfigurable cascades," in Proc. Int. Conf. Computer De- sign, 2001, pp. 388-393... H Qin,T Sasao,M Matsuura,... - 《電子情報通信学会技術研究報告. vlsi設計技術. vlsi design technologies》 被引量: 0发表: 2003年 Scalable IP Looku...
The authors formulate and analyze a controller synthesis problem for a plant which must meet certain hard real-time deadlines. In this timed input-output control problem, the plant is modeled by finite timed traces. The authors provide necessary and sufficient conditions for the existence of a tim...
1) Yosys - RTL Synthesis 2) blifFanout - High fanout net (HFN) synthesis 3) graywolf - Placement 4) qrouter - Detailed routing 5) magic - VLSI Layout tool 6) netgen - LVS 7) OpenTimer and OpenSTA - Static timing analysis tool 'vsdflow' is also the best utility ever written for ...
As discussed in Chapter 2, ESD is a very high current event. Therefore, ESD protection circuits should be able to handle a large amount of current without being destroyed. A number of semiconductor devices can be used to safely sink (source) this current
P Kakoty - 《International Journal of Vlsi Design & Communication Systems》 被引量: 24发表: 2011年 A REVIEW PAPER ON DESIGN AND SYNTHESIS OF TWO-STAGE CMOS OP-AMP DC gainlow-voltage single-stage CMOS opampoutput compliance voltage68 dB1.3 VThis paper presents a well defined method for the...
Simulations and VLSI synthesis results demonstrate that the proposed optimizations require a chip area of only 85 kGE to implement a 64-QAM SO MIMO detector for LTE capable of attaining almost ML performance with an SNR loss of only 0.85 dB. 展开 ...
A computer-aided design procedure for the automatic design of multilevel NAND gate logic networks as encountered in the synthesis of VLSI logic circuits is presented. A powerful technique using logic zero-one-interaction of permissible cubes is among the salient features in the synthesizing algorithm...
The method may include detecting one or more erroneous vectors in a plurality of vectors, detecting ... AJ Grichnik,TJ Felty,JR Mason 被引量: 0发表: 2010年 Three-dimensional image processing VLSI system with reconfigurable memory architecture and RAM/ROM synthesis design To enable flexible ...
Automatic Synthesis of a Serial Input Multiprocessor Array (Special Section on VLSI Design and CAD Algorithms) Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to ... LI,Dongju,KUNIEDA,... - 《...