The multilib compiler will have the prefix riscv64-unknown-elf- or riscv64-unknown-linux-gnu- but will be able to target both 32-bit and 64-bit systems. It will support the most common-march/-mabioptions, which can be seen by using the--print-multi-libflag on either cross-compiler. ...
set_module_property NAME riscv_timer set_module_property NAME orca_timer set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP "VectorBlox Computing Inc." set_module_property AUTHOR "VectorBlox Computing Inc." set_...
RISCV_MULTICORE_DISABLE; \ INIT_SATP; \ INIT_PMP; \ DELEGATE_NO_TRAPS; \ li TESTNUM, 0; \ la t0, trap_vector; \ csrw mtvec, t0; \ CHECK_XLEN; \ /* if an stvec_handler is defined, delegate exceptions to it */ \ la t0, stvec_handler; \ beqz t0, 1f; \ csrw stvec...
sw: $(ORCA_TEST_QEXES) $(RISCV_TEST_QEXES) simulate_%.tcl: simulate.tcl sed 's/system/system_$(*)/g' $< > $@ sim_waves_system_%.tcl: sim_waves_system.tcl sed 's/system/system_$(*)/g' $< > $@ test_%.log: system_%/simulation/mentor/msim_setup.tcl testall.tcl $(ORCA...
cd system_$*/simulation/mentor && vsim -c -do "source ../../../testall.tcl; run_tests $* {$(RISCV_TESTS) $(ORCA_TESTS)}" | egrep '(^[^#]|Error:|Error \(suppressible\):)' | tee ../../../test_$*.log cd system_$*/simulation/mentor && vsim -c -do "source ../../...
if [ -e $(*)/simulation/submodules/vblox_lve ]; then (cd $(*)/simulation/submodules/vblox_lve; for i in *.vhd; do if [ -f ../../../../ip/orca/lve/hdl/$$i ] ; then ln -sf ../../../../ip/lve/hdl/$$i $$i; fi; done; ); fi RISCV_TEST_QEXES ?= test/...
Expand Up @@ -15,8 +15,8 @@ OUTPUT_ARCH( "riscv" ) MEMORY { /* These should be autogenerated from BSP */ IMEM : ORIGIN = 0xC0000000, LENGTH = 64K DMEM : ORIGIN = 0xC0010000, LENGTH = 64K IMEM : ORIGIN = 0xA0000000, LENGTH = 64K DMEM : ORIGIN = 0xA0010000, LENGTH...
RISCV_MULTICORE_DISABLE; \ INIT_SATP; \ INIT_PMP; \ DELEGATE_NO_TRAPS; \ li TESTNUM, 0; \ la t0, trap_vector; \ csrw mtvec, t0; \ CHECK_XLEN; \ \ 1: csrwi mstatus, 0; \ init; \ EXTRA_INIT; \ EXTRA_INIT_TIMER; \ la t0, 1f; \ csrw mepc, t0; \ csrr a0, mha...