它接受一个std_logic_vector,并返回使用VHDL位运算符将所有位加在一起的结果。因此,如果向量中有X、Z、U等,你会得到其中“最强的”。 收藏分享票数4 EN 页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持 原文链接: https://stackoverflow.com/questions/2841744复制
The way you're going to work is writing Verilog or VHDL code, the tool helps you on most boring tasks: signal define for wire a/o reg, instance modules by connections with auto wire signals defined and easy name change, connect signals with regular expression, instance JSON and IPX...