// Code your testbench here 2 // or browse Examples 3 moduleOR_Gate_tb; 4 regA; 5 regB; 6 wireY; 7 integeri; 8 9 OR_Gateinst(.A(A), .B(B), .Y(Y)); 10 11 initialbegin 12 $dumpfile("dump.vcd"); 13 $dumpvars; ...