1 // Code your testbench here 2 // or browse Examples 3 module OR_Gate_tb; 4 reg A; 5 reg B; 6 wire Y; 7 integer i; 8 9 OR_Gate inst(.A(A), .B(B), .Y(Y)); 10 11 initial begin 12 $dumpfile("dump.vcd"); 13 $dumpvars; 14 #100 $finish; 15 end 16 17 in...