Exclusive-or gate for use in delay using transmission gate circuitry An exclusive-OR circuit is for use in a delay device outputting a signal delayed from an input signal. The exclusive-OR circuit comprises an odd number of inverters, an even number of inverters, and a two-input selector. ...
A low capacitance n-channel analog switch circuit, a p-channel analog switch circuit, and a full CMOS transmission gate (T-gate) circuit are described. Resistive decoupling can be used to isolate the switch or T-gate from AC grounds, such as one or more switch control signal inputs or ...
The circuit has an additional FET to sense the load current of a power FET. The power FET has a drain connected to a power supply, and a source connected to a load. The drain and the gate terminals of the two FETs are connected in parallel. A current corresponding to a division of ...
Making use of the beam fanning effect in a BaTiOcrystal, we propose two simple setups to perform the function of an optical image-combiner/OR-gate and an optical AND gate, respectively. The optical image combiner combines two patterns, mutually coherent or mutually incoherent, from two input ...
A door opening or gate opening device comprising a first drive shaft (1) adapted to be connected to a motor, a first worm (2) fitted to said first drive shaft (1), a second drive shaft (3) adapted to receive motion from said first drive shaft (1), a first toothed wheel (4) fitt...
A GPTR bit is applied to each of the clock macros 15-18 by the GPTR 10 and is used by the respective clock control macro to stop or gate-off the system clocks fed to functional units 11-14 when the respective GPTR bit is set to a binary “one” value. Accordingly, the chip 9 ...
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A Noisy-OR gate based fuzzy fault tree approach was used to estimate the probability of BGFC micro-leakage. Domain experts were invited to evaluate the probability level of basic events, which not only provided an opportunity to identify the weaknesses of the BGFC but also improved the reliabilit...
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