TI's I2C IO expander portfolio is made up of mostly Push-Pull CMOS output structures. Questions about using these devices as open drain instead of push pull has occasionally popped up, so can TI's IO expanders be configured to work for open drain applications...
These output configuration modes are either push-pull or open drain. This is shown below in the GPIO port output type register (GPIOx_OTYPER), which allows for the selection of either Output push-pull or Output open-drain. By default, all output GPIO pins are in push-pull state, unless ...
In open drain configuration, the logic behind the pin can drive it only to ground (logic 0). The other possible state ishigh impedance(Hi-Z). The implementation involves the use of a single transistor. If its drain terminal is open (the device is off) the pin is left floating to Hi-...
/// A workaround to set a pad's open drain configuration. /// /// This is a best effort until we can use the [`config`] API on /// the 1170. See the issue tracker for more details. /// https://github.com/imxrt-rs/imxrt-iomuxc/issues/28 pub(crate) fn set_open_drain<I...
The 'Open Drain' configuration is a requirement for some use cases. This means, the Drain (or the Collector with BJT) is left open, and needs an exernal load to VDD (or VCC). OD outputs form a 'wired OR', if connected together. For example, the I2C bus requires both bus pins (...
The situation could obviously be reversed, in that the button could connect to +3.3V (high) and a pull-down resistor could be used to keep the input low otherwise: The pull-up resistor configuration is however far more commonly used. Open Drain Outputs Some microcontroller outputs can be set...
Bonsai library for the Open Ephys Onix Acquisition System - Set I2C clock to 100 kHz for minscope configuration · open-ephys/bonsai-onix1@f13180d
SCL 47 IO, Open-Drain I2C Clock Input / Output Interface Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. I2CSEL 13 I, LVCMOS I2C Voltage Level Strap Option Tie to VDDIO with a 10-kΩresistor for 1.8-V I2C ...
The arbitration on the I2C bus is divided into two parts: the synchronization of theSCL lineand the arbitration of theSDA line. Synchronization of The SCL Line (Clock Synchronization) SCL synchronization is due to the logic function of the bus line “AND” (open-drain output), that is, as...
The backward compatibility configuration can be selected through the MODE_SEL pin or programmed through the device control registers (Table 8). The bidirectional control channel, bidirectional GPIOs, I2S, and interrupt (INTB) are not active in this mode. However, local I2C access to the ...