报的错误是dac_spi_i0/bit_cnt[4]_i_4的这个LUT有个输入悬空了,这个工程的逻辑比较简单,例化的嵌套也比较少,因此在schematic一层层找也很容易可以找到,但如果工程比较复杂,在很内部的一个LUT的输入悬空了,找起来就很费劲了。 笔者碰到的问题是在vivado的axi-interconnect ip中报了这个错误,而且是ip内部...
报的错误是dac_spi_i0/bit_cnt[4]_i_4的这个LUT有个输入悬空了,这个工程的逻辑比较简单,例化的嵌套也比较少,因此在schematic一层层找也很容易可以找到,但如果工程比较复杂,在很内部的一个LUT的输入悬空了,找起来就很费劲了。 笔者碰到的问题是在vivado的axi-interconnect ip中报了这个错误,而且是ip内部套了好...
在Vivado中,可能由于某些逻辑输入悬空而导致Implementation的opt_design时会错,比如: 报的错误是dac_spi_i0/bit_cnt[4]_i_4的这个LUT有个输入悬空了,这个工程的逻辑比较简单,例化的嵌套也比较少,因此在schematic一层层找也很容易可以找到,但如果工程比较复杂,在很内部的一个LUT的输入悬空了,找起来就很费劲了。
show_schematic [get_cells dac_spi_i0/bit_cnt[4]_i_4]
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