The microprocessor further includes a class storage circuit (80) for storing a class identifier corresponding to the portion of the non-cacheable data, as well as an input (TERMINATE) for receiving a terminate signal and an input (CLASS) for receiving a class signal. Lastly, the microprocessor...
A computer system is described including a CPU core, a memory device storing non-cacheable data, and a bus interface unit (BIU) coupled between the CPU core and the memory device. The CPU core accesses the memory device via the BIU. The BIU includes a stream read buffer, and the system...
A method for processing a non-cacheable write data request, a buffer and a node, the method comprising: after receiving a first non-cacheable write data request sent by a first processor, a buffer sends a first data buffer ID that is stored locally to the first processor; the buffer ...
The microprocessor includes a data storage circuit (62) for storing a portion of the non-cacheable data. The microprocessor further includes an address storage circuit (64) for storing an address corresponding to the portion of the non-cacheable data. Still further, the microprocessor includes a...
US5664148 1995年8月17日 1997年9月2日 Institute For The Development Of Emerging Architectures L.L.C. Cache arrangement including coalescing buffer queue for non-cacheable dataUS5664148 Aug 17, 1995 Sep 2, 1997 Institute For The Development Of Emerging Architectures L.L.C. Cache arrangement ...
Microprocessor comprising means for storing non-cacheable dataSteven D. KruegerJonathan H. Shiell
Microprocessor comprising means for storing non-cacheable dataKrueger, Steven D.Shiell, Jonathan H.
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2.2.3. MPU Sharing Data with FPGA 2.2.4. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA 2.2.4.1. Example 1: FPGA Reading Data from HPS SDRAM Directly 2.2.4.2. Example 2: FPGA Writing Data into HPS SDRAM Directly 2.2.4.3. Example 3: FPGA Readin...