1)non-overlap clock不交叠时钟 1.The two phasenon-overlap clockgenerator is one of the building blocks of the switch capacitor circuit.在开关电容电路中,一个必不可少的单元便是两相不交叠时钟产生单元,它产生不交叠时钟,控制节点不会同时被两个电压驱动;产生提前关断的时钟,以减少电荷注入效应的影响。
In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element.Wai Cheong Chan...
3) clock overlap 时钟重叠 1. The Tri-State-TG,positive edge sensitive,master-slave,register,during the clock overlap period of single-clock system,will lead to sample in the non-clock positive edge and the data output will change in the negative edge. 三态传输门正边沿主从寄存器,在单时钟...
The two phase non-overlap clock generator is one of the building blocks of the switch capacitor circuit. 在开关电容电路中,一个必不可少的单元便是两相不交叠时钟产生单元,它产生不交叠时钟,控制节点不会同时被两个电压驱动;产生提前关断的时钟,以减少电荷注入效应的影响。 更多例句>> 补充...
Clock generator for providing non-overlapping clock signals The non-overlap clock circuit of this invention is responsive to a variable input signal for producing a first and second output signal that vary respectively with phases opposite to and the same as the input signal. The circuit comprise....
US4877974 May 3, 1988 Oct 31, 1989 Mitsubishi Denki Kabushiki Kaisha Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequencyUS4877974 * 1988年5月3日 1989年10月31日 Mitsubishi Denki Kabushiki Kaisha Clock generator which generates a non-overlap clock ...
4) two-phase non-overlapping clock 两相非交叠时钟 5) overlapping nonmatching grid 交叠非叠匹配网格 6) overlap[英][,əuvə'læp] [美][,ovɚ'læp] 交叠 1. The criticaloverlapconcentration (C) and the critical entanglement concentration C_B of linear polystyrene (LPS) and branche...
[202]. Accordingly, the total number of coding sequences found on the lepidopteran W is extremely low, with little overlap between distantly related species [203,204,205]. Some families also seem to have experienced a secondary loss of the W [206], suggesting that the W chromosome is ...
The decoder includes a deadtime signal generator that produces a pulse at the rising edge of every input clock cycle. The decoder further includes a transmission gate responsive to the deadtime signal for selectively passing the decoder section output signal to a latch. The decoder further ...
However, undesirably some of the devices that are used to couple the clock signals to the diode devices (devices N22-N29) are in their breakdown regions because their gate voltage exceeds 3 volts when source-drain voltage is at 0 volts. This is particular severe for the devices in the ...