带冗余设计的Radix=1.864,non-binary redundancy的cdac电容权重为 543.3043 291.4723 156.3692 83.8891 45.0049 24.1442 12.9529 6.9490 3.7280 2.0000 1.0000 对上述两种cdac配置的sar adc进行仿真,得到如下结果,从对比结果看,redundancy减小了对建立时间的要求。编辑...
The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup ...
Within this work,an 11-bit differential non-binary Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) using non-binary capacitor array is presented.It has an input range of -1 to 1 V and has a sample rate of 5 MS/s.It operates with 1.8 V supplies.Simulation results...
This paper describes techniques for creating a low-power SAR ADC with an error-correcting non-binary successive approximation algorithm: (1) We propose a non-binary SAR ADC with two dynamic comparators; a low-power high-noise comparator for the first conversion stages, and a second comparator wi...
7 mm × 7 mm TQFP packages FUNCTIONAL BLOCK DIAGRAM AUX1 AUX2 REFIN REFOUT REFGND SDA SCL A1 A0 ADM1166 VREF SMBus INTERFACE VX1 VX2 VX3 VX4 VX5 VP1 VP2 VP3 VP4 VH AGND 12-BIT SAR ADC EEPROM CLOSED-LOOP MARGINING SYSTEM FAULT RECORDING DUAL- FUNCTION INPUTS (LOGIC INPUTS OR SFD...
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14.5fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90nm CMOS 来自 掌桥科研 喜欢 0 阅读量: 1 作者:JD Narasimaiah,MS Bhat 摘要: In this work, design technique and analysis of low-energy consumption successive ...
In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction....
They are also represented as up-to-233-bit-long binary numbers. The accelerator is based on the Montgomery kP algorithm using Lopez–Dahab projective coordinates [48]. The algorithm processes each bit of the scalar k iteratively from left to right (from its Most Signific...
The model is besed on Monte Carlo simulations applied to an analytical description of the ADC. Additional effects like charge injection and parasitic capacitance are included. The analytical basis covers different architectures with a fully binary weighted or series-split capacitor array. when comparing...