As an efficient interconnection network, Network-on-Chip (NoC) provides significant flexibility for increasingly prevalent many-core systems. It is desirable to deploy fault-tolerance in a dependable safety-critical NoC design. However, this process can easily introduce deeply buried flaws that ...
2.2.4 Routing Algorithms . . . . . . . . . . . . . . . . . . . 12 2.2.5 Network Behavior . . . . . . . . . . . . . . . . . . . . 13 3 Powering Networks on Chip 15 3.1 Reducing Power Consumption in Resources . . . . . . . . . . 15 3.1.1 Reducing ...
Photonic Network-on-Chips is a new generation of Network-on-Chips and has been proposed as a novel solution for the communication infrastructure of chip mu
Myers, A fault-tolerant routing algorithm for a network-on- chip using a link fault model, in: Proceedings of the Virtual Worldwide Forum on Electronic Design Automation VW-FEDA, Southampton, UK, 2011.J. Wu, Z. Zhang, and C. Myers, "A Fault-Tolerant Routing Algorithm for a Network- ...
Fault-tolerant routing algorithms are key concerns in Network-on-Chip (NoC) communication. This paper proposes a high performance fault-tolerant routing algorithm based on Fault-Tolerant-Routing (FTR) as a new solution to decrease delay of the messages over the on-chip interconnection mesh networks...
While such oblivious routing algorithms are easy to implement in hardware, they often inefficient job of balancing the load across the ... Al Areqi,Nadera Najib Qaid 被引量: 0发表: 2014年 ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers The advent of deep sub-micron...
2.3 Routing and arbitration The proposed switch supports different deterministic or adaptive routing algorithms such as XY [10], DyXY [12], and Odd-Even [13] used in the 2-D mesh topology. In addition, exhaustive round-robin [14] and priority- ...
networks on chiprouter architectureSummary: The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing predesigned small NoCs as subnets. In this paper we show that multi-level addressing is a cost-effective implementation option for hierarchical deadlock-free ...
来源会议 Proceedings of the 2007 International Conference on Embedded Systems & Applications, USA 2007, June 25-28, 2007, Las Vegas, Nevada, USA 2007/01/01 研究点推荐 heuristic Dynamic Spiral Mapping (DSM) Network on Chip Anticipating Routing Algorithm 引用走势 1957 被引量:1 站内活动 ...
In order to ensure compatibility, even if network portion is out of operation due to defects, the structural redundancy of the chip network is used with adaptive routing algorithms [25]. The distributed method of fault diagnosis makes it easier to assess the fault status of NoC switches and ...