In this chapter we focus on on-chip communication architecture design and introduce the reader to some essential concepts of NoC architecture. This is followed by a discussion on the commonly used power-saving techniques used for NoCs and the drawbacks and limitations of these techniques. We then...
Network-on-Chip Design Abstract Continuous transistor scaling has enabled computer architecture to integrate increasing numbers of cores on a chip. As the number of cores on a chip and application complexity has increased, the on-chip communication bandwidth requirement increased as well. Packet-switche...
With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Network-on-chip (NoC) has been proposed as an efficient solution to handle this distinctive challenge. In this thesis, we have explored the high performance NoC design for MPSoC ...
SoC:System on Chip,中文称为片上系统,主要是针对 ASIC 或者 chip 来讲的。在 ASIC 设计的早期,由于制造工艺和性能等的约束,大部分芯片都单纯地实现某个特定功能,如处理器内核、总线、内存控制器、蓝牙等都由各自独立的芯片分别实现,处理器之间的通信也以多颗芯片互连的方式实现。 随着制造工艺的提升,以及设计能...
HPCA21-Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures 摘要 在异构多核体系结构中,计算能力的提高提升了许多应用程序的并发执行。这需要一种灵活、高性能和节能的通信结构,能够处理同时运行多个应用程序所需的各种流量模式。如此严格的要求对当前的片上网络(NoC)设计提出了...
The paper presents a novel Optical Network on Chip (ONoC) relying on the multi-level optical layer design paradigm and called "OMNoC". The proposed ONoC relies on multi-level microring resonator allowing efficient light coupling between superposed waveguides. Such microring resonator avoids using ...
A Modular Network Interface Design and Synthesis Outlook In recent years, as System on Chip design research is actively conducted, a large number of IPs is included in a system based on a Network on Chip(NoC). Di... B Attia,A Zitouni,W Chouchenne,... - 《International Journal of Comput...
The Network-on-Chip (NoC) paradigm plays an essential role in designing emerging multicore processors. Three Dimensional (3D) NoC design expands the on-chip network vertically. To achieve high performance in a 3D NoC, it is crucial to reduce the access latency of caches and memories. In this...
In this paper we present a single FPGA chip implementation of a NOC based shared memory multiprocessor system with 24 processors connected to a main memory composed of 4 DDR2 banks. All the processors and DDR2 memories are connected to a NOC through Open
This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip ...