hMETIS hMETIS 高效的图划分算法. lemon lemon 图、网络中的高效建模和优化. SALT SALT 生成VLSI路由拓扑,在路径长度(浅度)和总线长(亮度)之间进行权衡. scipoptsuite SCIP 用于快速求解混合整数规划 (MIP) 和混合整数非线性规划 (MINLP) . mt-kahypar mt-kahypar 多线程超图划分器.我们...
config.h.in remove check for libreadline (not used) Nov 13, 2024 configure populating xschem git repo Aug 8, 2020 Repository files navigation README License xschem A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on ...
In VLSI design, the accuracy of timing analysis is very important to guide design optimization for timing closure and performance improvement. In the logic synthesis stage, it is difficult to predict the timing due to the lack of placement, and routing information. To improve the accuracy of tim...