nested+if+else+in+vhdl

2025-01-11 19:26:01

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Possible compilation error of nested if statements in VHDL

Or maybe it is a VHDL feature? Thank you in advance. frame_wren <= '1' if another_cnt = to_unsigned(12, another_cnt'length) else '0'; process(reset_n, clk, clk_ppu_en, frame_reg, frame_wren) begin if reset_n = '0' then frame_reg <= (others => '0'...
Possible compilation error of nested if statements in VHDL

Or maybe it is a VHDL feature? Thank you in advance. frame_wren <= '1' if another_cnt = to_unsigned(12, another_cnt'length) else '0'; process(reset_n, clk, clk_ppu_en, frame_reg, frame_wren) begin if reset_n = '0' then frame_reg <= (others => '0'...