对于典型的counter逻辑 always @(posedge sys_clk or negedge sys_rst_n) begin if(!sys_rst_n) counter <= 24'd0;//十进制0 else if(counter < led_time) begin flag_counter = 1'b0; counter <= counter + 1'b1; end else begin counter <= 24'd0; flag_counter = 1'b1; end end clk为什...
对于典型的counter逻辑 always @(posedge sys_clkornegedge sys_rst_n)beginif(!sys_rst_n) counter <=24'd0; //十进制0elseif(counter < led_time)beginflag_counter =1'b0; counter <= counter +1'b1;endelsebegincounter <=24'd0; flag_counter =1'b1;endend 在ModelSim仿真中,时钟是很严格,但是...