Nano-CMOS Gate Dielectric EngineeringFrank Schwierz
work function/ tungsten work function engineeringdual metal gate nanoCMOSbuffer layer technologysputtered aluminum nitridesilicon dioxide gate dielectricp-MOSFETA buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten ...
The measured 1 μm gate length implant free transistors feature high- κ gate dielectric, metal gate and low resistance ohmic contacts. They have a positive threshold voltage V T = 0.1 V and deliver a drive current I on, = 325 μA/ μm at V G = V D = 2 V. The Glasgow finite ...
The surface roughness effects are expected to be severe in future generations' devices with even thinner gate dielectric film and smaller size of the devices.Wong, HeiZhang, JieqiongIwai, HiroshiKakushima, KuniyukiNanomaterials (2079-4991)
New architectures and options are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By ...
On the other hand, there is an increase in the delay as the dielectric constant of the gate material, and consequently the load on the device, increases. Ultimately, this paper presents fast and accurate models for on-the-fly calculation of tunnelling current and delay with the aim of ...