Learn about designing a multiplexer in verilog with example code, specifically a 4x1 or 4 to 1 mux
If you change the testbench code to the following then I would expect glitching as two inputs are changing at once and it transits through a state with a different output. Interestingly, this produces glitches that are 7ns in size compared to the 1ns glitches I was seeing initially. `...
If you change the testbench code to the following then I would expect glitching as two inputs are changing at once and it transits through a state with a different output. Interestingly, this produces glitches that are 7ns in size compared to the 1ns glitches I was seeing initially. `...