网络多核心 网络释义 1. 多核心 此外,他也指出,德仪的OMAP 5处理器采多核心(multicore architecture)架构,除内建2颗ARM Cortex A15处理器,也加入2颗… www.36ic.com|基于2个网页 例句
Electrical engineering Architecture-aware hard-real-time scheduling on multi-core architectures SOUTHERN ILLINOIS UNIVERSITY AT CARBONDALE Dimitrios Kagaris ShekharMayankThe increasing dependency of man on machines have led to increase computational load on systems. The increasing computational load can be ...
Operating point management in multi-core architecturesdoi:CN101111814 A管理工作点的系统和方法用来确定多个处理器核中的活性核数量. System and method for managing the operating point of the plurality of processor cores to determine the number of active nuclei. 根据活性核数量选择至少一个活性核的最大...
关键词:computer architecture(计算机体系结构), multi-core processors(多核处理器), cache hierarchies(缓存层次结构), shared and private caches(共享缓存和私有缓存), non-uniform cache access (NUCA)(非一致性缓存访问), quality-of-service(QoS,服务质量), cache partitions(缓存分区), replacement policies(替...
PFQ is a functional framework designed for the Linux operating system built for efficient packets capture/transmission (10G, 40G and beyond), in-kernel functional processing, kernel-bypass and packets steering across groups of sockets/end-points. It is highly optimized for multi-core architecture, ...
This paper proposes a reconfigurable multi-core architecture, called hyperscalar that enables many scalar cores to be united dynamically as a larger superscalar processor to accelerate a thread. To accomplish this, we propose the virtual shared register files (VSRF) that allow the instructions of a...
Hardware Architecture Optimized for Iris Recognition One of the remaining problems in iris recognition is the implementation of its efficient hardware systems. The difficulty arises from the fact that the met... K Grabowski,A Napieralski - 《IEEE Transactions on Circuits & Systems for Video Technology...
Homogeneous or heterogeneous architecture? The answers to these questions are not unique and mostly will depend on the application and its purpose. On the other hand, it is not guaranteed that the application will benefit from more cores at all. The computational workload of the application needs...
Composable Platform-Aware Embedded Control Systems on a Multi-core Architecture. JJV Payan,DD Goswami,KK Goossens 被引量: 7发表: 2015年 Time-Triggered Architecture The next generation of automotive control systems will consists of a set of networked electronic control units (ECUs) that operate in...
It is becoming increasingly evident that multi-core chip architecture are emerging as a solution to efficiently amortizing the ever-growing number of transistors on a chip. However the success of such multi-core chips depends on the adva... A Douillet,GR Gao - International Conference on Parallel...