A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of signal values. An illustrative embodiment of the multi-input comparator includes N inputs and generates an output corresponding to the maximum or minimum value in a set of ...
A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of signal values. An illustrative embodiment of the multi-input comparator includes N inputs and generates an output corresponding to the maximum or minimum value in a set of si...
CONSTITUTION:The input data E-H are supplied to a latch circuit 3 and stored there. The latch data 9 undergoes the comparison of levels through a 2-input comparator 4 in terms of the combination to select two out of four pieces of data. Then a level deciding circuit 5 produces ...
United States Patent US6515533 Note: If you have problems viewing the PDF, please make sure you have the latest version ofAdobe Acrobat. Back to full text
3) multi-input 多端输入,多输入4) output comparator 输出比较器5) unused inputs 多余输入端 1. There are some unused inputs in practical use of TTL gate circuit. TTL门电路在实际应用中,往往存在多余输入端,对多余输入端如何处理,处理的方法不同,会对电路性能产生什么影响,这是值得研究分析的...
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µs 2 ns 1 input signal slope dVCS/dt = 300mV/µs 2 4.4.5 Characteristics of the Zero Crossing Input ZCD Table 24 Zero-Crossing Comparator Characteristics Parameters Symbol Zero-crossing threshold Comparator propagation delay Input voltage negative clamping level VZCTHR tZCPD –VINPCLN Min. ...
import java.util.Comparator; import java.util.List; import java.util.UUID; import javax.servlet.http.HttpServletRequest; import org.apache.commons.io.FilenameUtils; import org.springframework.web.multipart.MultipartFile; /** * 图片工具类
a comparator coupled to receive the integrated sum and a reference level signal, the comparator outputting a logic level signal as a function of the received reference level signal; a digital logic circuit in response to an external clock signal, the digital logic circuit receiving the logic level...
Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an ...