第8 章 使用 ModelSim 进行设计仿真 ModelSim为HDL仿真工具,我们可以利用该软件来实现对所设计的VHDL或Verilog程 序进行仿真,支持IEEE常见的各种硬件描述语言标准.可以进行两种语言的混合仿真,但 推荐大家只对一种语言仿真.ModelSim常见的版本分为ModelSim XE和ModelSim SE两种, ModelSim版本更新很快,目前最新版本为 5.8 ...
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release ;mvc_lib = $MODEL_TECH/../mvc_lib UNISIMS_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\unisims_ver UNIMACRO_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\unimacro_ver UNI9000_VER = C:\Xilin...
UNIMACRO_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\unimacro_ver UNI9000_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\uni9000_ver SIMPRIMS_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\simprims_ver XILINXCORELIB_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\XilinxCoreLib_ver SECUREIP = C:\Xilinx\1...
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release ;mvc_lib = $MODEL_TECH/../mvc_lib UNISIMS_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\unisims_ver UNIMACRO_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\unimacro_ver UNI9000_VER = C:\Xilin...
; in VHDL or Verilog format.; For VHDL, PathSeparator = /; For Verilog, PathSeparator = .; Must not be the same character as DatasetSeparator.PathSeparator = / ; Specify the dataset separator for fully rooted contexts.; The default is ':'. For example, sim:/top; Must no...
(112): (vcom-1195) Cannot find expanded name "work.stratixiv_hssi_components".# ** Error: ./altera/stratixiv_hssi_atoms.vhd(112): Unknown expanded name.# ** Error: ./altera/stratixiv_hssi_atoms.vhd(114): VHDL Compiler exiting# ** Error:...
22、始化文件modelsim.ini文件发现其库映射设置如下:Librarystd= $MODEL_TECH/./std ieee = $MODEL_TECH/./ieee verilog = $MODEL_TECH/./verilog vital2000 = $MODEL_TECH/./vital2000 std_developerskit = $MODEL_TECH/./std_developerskit synopsys = $MODEL_TECH/./synopsys modelsim_lib = $MODEL_TEC...
verilog = $MODEL_TECH/../verilog ... vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib sv_std = $MODEL_TECH/../sv_std mtiAvm = $MODEL_TECH/../avm mtiOvm =...
我用来仿真VHDL写的工程,对于VERILOG的不清楚。我也在问别人如何用MODELSIM进行混合编程的工程?对于这种工程我现在只能用ACTIVEHDL仿真。 3.如何在modelsim中指定Altera的仿真库? 我就是按照精华区那个帖子上说的把quartusedasim_libaltera_mf.v、lpm生成的afifo.v、testbench.v放在一起编译,照着做还是提示如下错误实...
# ** Error: D:/caiyang/rev_1/caiyang_1.vhd(14): VHDL Compiler exiting library ieee, acex2k;use ieee.std_logic_1164.all;use ieee.numeric_std.all;library synplify;use synplify.components.all;use acex2k.acex2k_components.all;~~~就是提示找不到这个东西，这是用synplify综合后的文件的前面...