** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x9c>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): VHDL Compiler exiting...
However, when i try to compile this fft_pack_fft_90.vhd file, following error messages displayed# ** Error: C:/altera/Project/FFT_h/fft-library/fft_pack_fft_90.vhd(1): near "<byte 0x8b>": illegal character found in source# ** Error: C:/altera/Project/FFT_h/fft-library/fft_pack...
At the beginning , I did what you said to me (ddr_par.v without module-endmodule), but i got error message : global declarations are illegal in verilog 2001 syntax. From other forum , there's someone who said that most of verilog source code have module-endmodule. I know it but i...
** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x9c>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): VHDL Compiler exiting...
** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x9c>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): VHDL Compiler exiting...
** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x9c>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): VHDL Compiler exiting...
** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x9c>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): VHDL Compiler exiting...
** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x9c>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): VHDL Compiler exiting...
At the beginning , I did what you said to me (ddr_par.v without module-endmodule), but i got error message : global declarations are illegal in verilog 2001 syntax. From other forum , there's someone who said that most of verilog source code have module-endmodule. I know it bu...
At the beginning , I did what you said to me (ddr_par.v without module-endmodule), but i got error message : global declarations are illegal in verilog 2001 syntax. From other forum , there's someone who said that most of verilog source code have module-endmodule. I know...