_mclk_t; begin MCLK_PROC: process (clock, mclk_r_in) begin if rising_edge (clock) then mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: Unex...
Apart from this bug I get plagued by the obscure "Fatal: Unexpected signal: 11." error on about every other project I try to simulate in RTL. So I revert to the Timimg Simulation as this always seems to work, be it a lot slower than RTL Simulation. I guess ModelSim has no problem...
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 19:54:38 on Oct 05,2018 # vlog -reportprogress 300 ./../submodules/mentor/apn_fft_mult_cpx_1825.v -work fft_ii_0 # ** Fatal: Unexpected signal: 11. # ** ...
_mclk_t; begin MCLK_PROC: process (clock, mclk_r_in) begin if rising_edge (clock) then mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: Unexp...
_mclk_t; begin MCLK_PROC: process (clock, mclk_r_in) begin if rising_edge (clock) then mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: Unexp...
_mclk_t; begin MCLK_PROC: process (clock, mclk_r_in) begin if rising_edge (clock) then mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: Unex...
_mclk_t; begin MCLK_PROC: process (clock, mclk_r_in) begin if rising_edge (clock) then mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: ...
_mclk_t; begin MCLK_PROC: process (clock, mclk_r_in) begin if rising_edge (clock) then mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: Unexp...
_mclk_t; begin MCLK_PROC: process (clock, mclk_r_in) begin if rising_edge (clock) then mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: Unex...
_mclk_t; begin MCLK_PROC: process (clock, mclk_r_in) begin if rising_edge (clock) then mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: Une...