用VerilogHDL纯手工打造的5级IA-32解码流水线(仅decode就用了5级流水,非完整CPU核心) 每一个stage功能如下 - 解码lengcy prefix - 解码opcode(1,2,3 bytes)三种可能性 - 解码field,编码在primary opcode中的获得w,s,greg,sreg - 解码mod r/m和s-i-b(scale-index-base) - 解码
First, since you want to do an all HDL design your sources are missing at least one key element... a Verilog testbench. Part of the design process is verification, and at a minimum behavioral simulation is one part of verification. Simulation will help figure out what's going on with yo...