// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports .DADDR(DADDR), // 7-bit input: DRP address .DCLK(DCLK), // 1-bit input: DRP clock .DEN(DEN), // 1-bit input: DRP enable .DI(DI), // 16-bit input: DRP data .DWE(DWE), // 1-bit input: DRP write enabl...
I have made a version of the design (IF .. GENERATE) which does not use drp, but allows me to reset to MMCM from a software register (clocked by the same 100 MHz clock as I was using for the AXI DRP interface) This has passed 10000 passes of reseting the MMCM. So I suggest th...
This patch addresses the issue where the MMCM output clocks hold their state for several clock cycles and then return to normal operation when using the DRP functionality. Solution Overview Date: 11/05/2013 File Name: AR_58276_2013_3_MMCM.zip ...
This patch is only for the 2013.3 tool and is to be repaired in the 2013.4 tool. This patch addresses the issue where the MMCM output clocks hold their state for several clock cycles and then return to normal operation when using the DRP functionality....
// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports .DADDR(DADDR), // 7-bit input: DRP address .DCLK(DCLK), // 1-bit input: DRP clock .DEN(DEN), // 1-bit input: DRP enable .DI(DI), // 16-bit input: DRP data ...