// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports .DADDR(DADDR), // 7-bit input: DRP address .DCLK(DCLK), // 1-bit input: DRP clock .DEN(DEN), // 1-bit input: DRP enable .DI(DI), // 16-bit input: DRP data .DWE(DWE), // 1-bit input: DRP write enabl...
I have made a version of the design (IF .. GENERATE) which does not use drp, but allows me to reset to MMCM from a software register (clocked by the same 100 MHz clock as I was using for the AXI DRP interface) This has passed 10000 passes of reseting the MMCM. So I suggest th...
// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports .DADDR(DADDR), // 7-bit input: DRP address .DCLK(DCLK), // 1-bit input: DRP clock .DEN(DEN), // 1-bit input: DRP enable .DI(DI), // 16-bit input: DRP data .DWE(DWE), // 1-bit input: DRP write enabl...