.parent = &mmc_clk, .enable_reg = AM33XX_CM_PER_MMC2_CLKCTRL, .enable_bit = AM33XX_MODULEMODE_SWCTRL, .ops = &clkops_omap2_dflt, .recalc = &followparent_recalc, }; 也就是192/2=96MHz 我现在接一个WIFI设备无法工作,想尝试降低MMC2的频率到48MHz 或 24MHz,不知道是否可以在不影响M...
The get_mmc_clk ops is expected to set a clock rate and return the configured rate as an unsigned value. However, if clk_set_rate fails, e.g. using a fixed rate clock, a negative error value is returned. The mmc core will treat this as a valid unsigned rate and tries to configure...
Contains settings that control clock main_nand_sdmmc_clk generated from the C4 output of the Main PLL. Only reset by a cold reset.
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+++ b/drivers/mmc/core/Kconfig @@ -1,13 +1,3 @@ # # MMC core configuration # - -config MMC_CLKGATE - bool "MMC host clock gating" - help - This will attempt to aggressively gate the clock to the MMC card. - This is done to save power due to gating off the logic and bus...
> MMC_CLKGATE was once invented to save power by gating the bus clock at > request inactivity. At that time it served its purpose. The modern way to > deal with power saving for these scenarios, is by using runtime PM. > > Nowadays, several host drivers have deployed runtime PM, bu...
cat mmc1/ios clock: 48000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 9 (mmc HS200) signal voltage: 0 (1.80 V) driver type: 0 (driver type B) ...
Re: 新手上路内核启动过程中一直出现 sunxi-mmc 1c0f000.mmc: fatal err update clk timeout 报错 可能这组TF卡引脚和他的复用功能冲突, 详细情况查看你的dts: https://whycan.cn/t_636.html#p13068 taobao: V3s/F1C100s/F1C200s/D1-H/D1s/T113-S3/XR32/XR829/A523/A133/H133/V831/V851s/V853 ...
Hi. Having this error when building with the latest dev or stable kernel, then it works for a little while, but when trying to install some packages, then, after a while, Card stuck in programming state! mmc_do_erase appears in the code...
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