.parent = &mmc_clk, .enable_reg = AM33XX_CM_PER_MMC2_CLKCTRL, .enable_bit = AM33XX_MODULEMODE_SWCTRL, .ops = &clkops_omap2_dflt, .recalc = &followparent_recalc, }; 也就是192/2=96MHz 我现在接一个WIFI设备无法工作,想尝试降低MMC2的频率到48MHz 或 24MHz,不知道是否可以在不影响M...
.parent = &mmc_clk, .enable_reg = AM33XX_CM_PER_MMC2_CLKCTRL, .enable_bit = AM33XX_MODULEMODE_SWCTRL, .ops = &clkops_omap2_dflt, .recalc = &followparent_recalc, }; 也就是192/2=96MHz 我现在接一个WIFI设备无法工作,想尝试降低MMC2的频率到48MHz 或 24MHz,不知道是否可以在不影响M...
16 changes: 15 additions & 1 deletion 16 include/dwmmc.h Original file line numberDiff line numberDiff line change @@ -163,7 +163,21 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); unsigned int (*get_mmc_clk)(...
26 问题补充：我示波器测出来mmc2_clk的波形为48MHz的正弦波 是否可以把频率降低为24MHz？是否可以改为...
+++ b/drivers/mmc/core/Kconfig @@ -1,13 +1,3 @@ # # MMC core configuration # - -config MMC_CLKGATE - bool "MMC host clock gating" - help - This will attempt to aggressively gate the clock to the MMC card. - This is done to save power due to gating off the logic and bus...
Just for clarification, when DevKit is turned on, the SDIO-CLK gets always the same value than MMC memory clock. In this case 446 KHz. When MMC1 ( SDIO ) is initialized, the SDIO-clock changes to its correct value which is determined in "drivers/mmc/core/sdio.c" in function mmc_set...
> MMC_CLKGATE was once invented to save power by gating the bus clock at > request inactivity. At that time it served its purpose. The modern way to > deal with power saving for these scenarios, is by using runtime PM. > > Nowadays, several host drivers have deployed runtime PM, bu...
static int meson_mx_sdhc_gate_clk_hw_register(struct device *dev, const char *name_suffix, struct clk_hw *parent, struct clk_hw *hw) struct clk_hw *hw, struct clk_bulk_data *clk_bulk_data, u8 bulk_index) { struct clk_parent_data parent_data = { .hw = parent }; ...
cat mmc1/ios clock: 48000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 9 (mmc HS200) signal voltage: 0 (1.80 V) driver type: 0 (driver type B) ...
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