package 选 FG320,speed 选-4.开发语言选 VHDL。如下图点击next,会看到工程的总结Project Summary。如下图点击Finish就创建好了一个新的工程。这时ISE王界面会出现我们新建的TEST工程。如下 图。不过这时我们的工程是空的。三:为我们的工程添加一个microblaze软核了。如下图 I □却X□ H = X fti x o? L...
and VHDL. For IC devices implementing synchronized digital circuits, the hardware descriptor code may include register transfer level (RTL) code to provide an abstract representation of the operations of the synchronous digital circuits. For other types of circuitry, the hardware descriptor code may in...