namic memory disambiguation. We move away from the conventional exact disambiguation strategy and adopt an opportunistic method: we allow loads and stores to access an L0 cache as they are issued out of programorder, hoping that with such a laissez-faire approach, most loads actu- ...
The LSQ is decoupled from the D-KIP in the same sense as a Decoupled Access-Execute Architecture [15]. In the D-KIP, the Address Processor needs to interface the Cache Processor and the Memory ...S. Sethumadhavan et al., "Scalable Hardware Memory Disambiguation for High ILP Processors,"...