Method and system for detecting and correcting errors while accessing memory devices in microprocessor systemsSystems and methods for ensuring data integrity in a data processing system are disclosed. The method may include monitoring when data for a specified device is available for error correction ...
1.A method for ensuring data integrity in a data processing system, the method comprising:monitoring when data for a specified device is available for error correction code generation;receiving a first indication of said specified device, a second indication of said data and a third indication of...
Developments during 1990 and future trends in solid-state devices are discussed. 1990 saw the commercial introduction of microprocessor chips containing more than 1 million transistors, and 1991 will probably see microprocessor chips with well over 2 million transistors. Processor speeds are keeping pace...
An electronic appliance having a microcomputer, peripheral devices controlled by the microcomputer, a main battery acting as power source, and a backup battery for backing up the main battery. Checking is made of whether the main battery... N Taniguchi,S Tominaga,K Yamamoto,... - US 被引量...
Rambus Dynamic RAM.DRDRAM is a memory subsystem that promised to transfer up to 1.6 billion bytes per second. The subsystem consists of RAM, the RAM controller, the bus that connects RAM to the microprocessor and devices in the computer that use it. ...
Programmable logic devices B.HOLDSWORTHBSc (Eng), MSc, FIEE,R.C.WOODSMA, DPhil, inDigital Logic Design (Fourth Edition), 2002 11.7Memory addressing One typical application formemory chipsis to provide storage for programs and data in a microprocessor system. It is common practice for a number...
A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response... JH Shin,Won Hyung Song,Jong Min Lee,... 被引量: 2发...
NH Fujioka - 《電子情報通信学会技術研究報告. 集積回路. integrated circuits and devices》 被引量: 0发表: 2002年 Microcomputer, microprocessor, and debugging peripheral device for core processor integrated circuit PURPOSE: To execute the background mode processing by an existing CPU by coupling a deb...
In long devices the electric field in the memory channel shows two peaks (Fig. 4.32(a)): the first peak is located in the gap, due to the difference between the memory gate and the select gate potentials; the second peak is created at the channel source junction. As the gate length is...
memory devices are highly pipelined. Attributes of the memory hierarchy described above are all structured to try to ensure that the application does not directly experience the latency of a DRAM transaction. To that end, in addition to thecache structure, some platforms have pre-fetchers. A pre...