The present invention is particularly directed to the enabling of a refresh cycle for a dynamic memory chip at a period in the fetch cycle, for example, of a type 8085 microprocessor, when the normal timing of the chip does not permit addressing of the memory. Specifically, in...
A frequently used integrated circuit for general use, known as a microprocessor, can also be used for realizing the device in accordance with the invention. A plurality of "peripheral" circuits in the form of memories (ROM, RAM), input/output circuits etc. can then be accommodated on the ...
5060186 High-capacity memory having extended addressing capacity in a multiprocessing system 1991-10-22 Barbagelata et al. 364/200 5055999 Multiprocessor digital data processing system 1991-10-08 Frank et al. 395/425 5025365 Hardware implemented cache coherency protocol with duplicated distributed directo...
address bus means connected to said processors and said memory for addressing appropriate memory locations; wherein said data bus means comprises a first data bus and a second data bus, said first data bus connecting: a bidirectional port on said high speed processor; ...
The present invention is particularly directed to the enabling of a refresh cycle for a dynamic memory chip at a period in the fetch cycle, for example, of a type 8085 microprocessor, when the normal timing of the chip does not permit addressing of the memory. Specifically, in the fetch ...