HW_WR_REG32 (SOC_CORE_PAD_IO_REGISTER+CTRL_CORE_PAD_SPI1_D0、0x000C0000); HW_WR_REG32 (SOC_CORE_PAD_IO_REGISTER+CTRL_CORE_PAD_SPI1_CS0、0x00060000); #IF已定义(SOC_TDA2XX)||已定义(SOC_TDA2PX) HW_WR_REG32 (SOC_CORE_PAD_IO_REGISTER+CTRL_CORE_PAD_SPI1_...
linux-4.14.40/sound/soc/soc-core.c Regards, Pavel Hi Pavel, Thank you, soc-core.c looks very useful in finding the issue. The Beaglebone-Black is stock, then interfaced through P9 to my custom board. I am using the McASP is in master mode on ...
In this case, designers took advantage of the BeagleBone development board with a Sitara AM335x processor featuring an Arm Cortex-A8 core running Linux, the user interface and model processing while the PRU performed the real-time control of five stepper motors. A shared region of memory was ...
Check AM335x TRM, section 22.3.8.1 Burst Transfer Mode. In TDM mode, if the transmit/receive bit is active, the McASP functions normally during that time slot; otherwise, the McASP is inactive during that time slot; no update to the buffer occurs, and no event is generated. Transmit ...