FPGA Implementation of High Speed Architecture for Max Log Map Turbo SISO DecoderThis paper presents a turbo soft in soft out (SISO) decoder based on Max-log-map algorithm using sliding window techniques. The proposed architecture is based on branch metric normalization to improve the speed of ...
一种改进的Turbo码译码算法及其FPGA实现 为有效降低Turbo码在硬件实现时的译码复杂度并减少其存储资源消耗,将现有Turbo码译码算法中Log-MAP算法和Max-Log-MAP算法进行融合改进,提出一种适于并行计算的改进Max... 卜祥元,杨行,邱源,... - 《北京理工大学学报》 被引量...
被引量: 0发表: 2013年 ModifiedMax-Log-MAP暨滑動視窗演算法之FPGA渦輪解碼器設計與研究 典型的BICM(比特交织编码调制,Bit interleaved Coded Modulation)系统中,为了逼近信道容量,接收及解调端通常使用软入软出(SISO, Soft In Soft Out)的解映射及解码算法... 郭耀隆 被引量: 0发表: 2004年 加载更多来源...
Turbo码Max-Log-MAP算法研究及其实现
FPGA Implementation of an Efficient High Speed Max-log-MAP Decoderdoi:10.1109/icacci.2018.8554365Aishwarya AmbatKarthi BalasubramanianB. YamunaDeepak MishraIEEEAdvances in Computing and Communications
首先分析了Turbo码的Log-Map和Max-Log-MAP译码算法,然后对符合CCSDS标准的Turbo码的Max-Log-MAP译码算法在Matlab上进行仿真验证,最后在Xilinx FPGA平台xc4vlx100上硬件实现了Max-Log-MAP算法。doi:CNKI:SUN:DZJI.0.2013-05-016夏慧宁中国电子科技集团公司吉磊中国电子科技集团公司CNKI;WanFang大众科技夏慧宁,吉磊....
Mao-Hsiu H,Jhin-Fang H.High Performance and Low Complexity Max-Log-MAP Algorithm for FPGA Turbo Decoder.Advanced Communication Tech-nology,ICACT. 2005Mao-Hsiu H,Jhin-Fang H.High Performance and Low Complexity Max-Log-MAP Algorithm for FPGA Turbo Decoder. Advanced Communication Tech-nology,ICACT ...
FPGAThis paper presents an efficient and reduced memory design and FPGA implementation of Max-Log-maximum a posteriori (MAP) turbo decoder for CCSDS telemetry channel coding standard. Efficient implementation comes from using integer arithmetic, sliding window(SW) technique and compact hardware and ...
FPGAASICEmergent wireless communication standards, which are employed in different transmission environments, support various modulation schemes. High-order constellations are targeted to achieve high bandwidth efficiency. However, the complexity of the symbol-by-symbol MaximumA Posteriori(MAP) algorithm ...