The A_FULL bit will be set when the FIFO contains 128 minus FIFO_A_FULL[6:0] FIFO_STAT_CLR (Address 0x0A) items. When the FIFO is almost full, if the A_FULL_EN The FIFO_STAT_CLR bit defines whether the A-FULL mask bit in the Interrupt_Enable register (0x03) is set, then ...