To run this example, perform these steps:Configure the deep learning processor and generate IP core. Model the design under test (DUT), including preprocessing modules for calculating the amplitudes and handshaking logic with the deep learning processor. Generate and deploy the bitstream on the FP...
HDL Coder®to generate IP corestargeting programmable logicof SoC FPGAs. SoC Blockset™to extend the ability of Simulink to model, simulate, and analyze SoC FPGA architectures, including communication with off-chip DDR memories and I/O devices. SoC Blockset accounts for latency between the comp...
Set theADC/DAC Samples-Per-Clock-Cycleparameter to the required sample rate. Set theDMA AXI4-Stream TData Bit-Widthparameter to32,64, or128bits. The number of samples per clock, or DMA data width, affect the data type of the signal lines to reflect the word length. For example, when...
FPGA Data Capture storage type: Specify the memory type for storing captured data as one of these options: Internal memory (default) — This memory type uses the internal BRAM resources of the FPGA to store captured data. External memory— This memory type uses external DDR, or any memory bl...
This example shows how to create, compile, and deploy a long short-term memory (LSTM) network trained on waveform data by using the Deep Learning HDL Toolbox™ Support Package for Xilinx FPGA and SoC. Use the deployed network to predict future values by using open-loo...
An example result is shown in the figure when looping back through the FPGA. The plotted figure shows the real part of the output data from the DUT algorithm when the gain value is set to 1 and then when the gain value is set to 4....
Use the custom bitstream to deploy the pretrained ResNet-18 network to your target FPGA board. hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2023.1\bin\vivado.bat'); dlhdl.buildProcessor(hPC_optimized); Algorithms expand all InputMemorySize and OutputMemory...
Aresainl-ttriomduecseydsbteemforses, ubecshidaessuthseinsgterloeowmleatvcehlinlagnaglguoargitehsm(se,.g. C, Robotics 2016, 5, 24 6 of 16 Assembler) using multi-processor boards for parallel computing or coding the algorithm in a field programmable gate-array (FPGA) [13,14]. Inputs and...
In this example, you can write the captured samples of an analog-to-digital converter (ADC) into external programmable logic (PL) DDR4 memory, read the samples from the PL DDR4 memory, and send them to the processor to display. A tone signal is generated in FPGA using a numerically ...
In this example, the target FPGA board is the Xilinx ZCU102 SoC board. The bitstream uses a single data type. Get hW=dlhdl.Workflow(Network=trainedSN,Bitstream='zcu102_single',Target=hTarget) hW = Workflow with properties: Network: [1×1 DAGNetwork] Bitstream: 'zcu102_single' Processor...