Cora z7, board files, M_AXI_GP0_ACLK not connected to clock...
If you only have the Zynq processor in your block design you will need to connect the FCLK_CLK0 to the M_AXI_GP0_ACLK as I have done in the attached screen shot. Please attach a screen shot of your block design if this does not fix the issue. ...