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The right-half-plane zero of an IBB topology is at its lowest frequency at minimum input voltage. However, it does not appear at low frequency for a –5-V output and has minimal effect on the loop response for this application. In an inverting buck-boost configuration, the input capacitor...
9.2.2.2.6 Other Considerations Short RBOOT to CBOOT and connect VLDOIN to the power stage GND terminal (corresponding to VOUT1, VOUT2 of the module) for best efficiency. The right-half-plane zero of an IBB topology is at its lowest freqeuncy at minimum input voltage and highest load ...