Solved: I'm using S32K148-EVB (nxp.s32k148evb-q176). I am testing the example to use uart, but the rx signal from lpuart1 is strange. * Connection:
Hello, I have some questions about LPUART1 of 'S32K142'.I use it with LIN transceiver 'ATA663211'. I use it to be master. My transmit function
Solved: iMX93(9332 soc), pinmux the gpio_io04 & gpio_io05 as LPUART6_TX & LPUART6_RX. dts: &lpuart6 { pinctrl-names = "default"; pinctrl-0
LPUART1 echoes RX signal at 115200 bps When an 's' char is received, the MCU enters VLPS. A falling edge of the RX signal brings the MCU from VLPS via LPUART RXEDGIF interrupt. BUS_CLK can be monitored at CLKOUT PTD14. In VLPS, BUS_CLK is gated off. ...
Hi, I'm developing a custom board using ls1028a. I added lpuart to dtsi to use lpuart, lpuart2: serial@2280000 { compatible =
If RXWATER is greater than zero (say, N), then my LPUART ISR will not trigger until N+1 characters have been received. Per the manual, I had set RXWATER to 1; this manifested as a bug of the FIFO always retaining the last character received, and only delivering prior characters...
If RXWATER is greater than zero (say, N), then my LPUART ISR will not trigger until N+1 characters have been received. Per the manual, I had set RXWATER to 1; this manifested as a bug of the FIFO always retaining the last character received, and only delivering prior characters to ...
Hello, I have some questions about LPUART1 of 'S32K142'.I use it with LIN transceiver 'ATA663211'. I use it to be master. My transmit function
iMX93(9332 soc), pinmux the gpio_io04 & gpio_io05 as LPUART6_TX & LPUART6_RX. dts: &lpuart6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart6>; status = "okay"; }; pinctrl_uart6: uart6grp { fsl,pin = < MX93_PAD_GPIO_IO04__LPUART6_TX ...
解決済み: iMX93(9332 soc), pinmux the gpio_io04 & gpio_io05 as LPUART6_TX & LPUART6_RX. dts: &lpuart6 { pinctrl-names = "default"; pinctrl-0 =