yes, LPSPI_DRV_MasterTransferBlocking can be used for that. If you see bigger delay between each bytes you can try to use LPSPI_DRV_MasterSetDelay function which configures the LPSPI master mode bus timing delay options (SCK to PCS, PCS to SCK and Delay between Transfers) BR...
uint8_t tx_buf[3]; uint8_t masterDataReceive[3]; lpspi_state_t masterStateSPI0; LPSPI_DRV_MasterInit(SPI0, &masterStateSPI0, &SPI0_MasterConfig1553); LPSPI_DRV_SetPcs(SPI0,LPSPI_PCS0,LPSPI_ACTIVE_LOW); holt_6135_reset(); tx_buf[0] = enMAP1; tx_buf[1] = 0x00; tx_...
LPSPI_DRV_MasterTransfer(INST_LPSPI_1, master_buffer.tx, master_buffer.rx, 5); delayCycles(100); LPSPI_SetTxCommandReg(LPSPI0, &txCmdCfgSet ); the picture is add delay,it's ok this picture is not add delay, after transfer 4 data,the PCS is negate. Is this because the FIFO siz...
Hi NXP community, I have a problem with the LPSPI0 transfers which explain below. When I set LPSPI0 as master to transmit 4 bytes at 4,8MBaudrate
yes, LPSPI_DRV_MasterTransferBlocking can be used for that. If you see bigger delay between each bytes you can try to use LPSPI_DRV_MasterSetDelay function which configures the LPSPI master mode bus timing delay options (SCK to PCS, PCS to SCK and Delay between Transfers) BR, Petr 0 ...
void delay_test(int count) { while(count > 0) count--; } void spi_test() { uint8_t masterDataSend[3]; uint8_t masterDataReceive[3]; int count = 0; int flag = 0; while(1) { count++; if(count > 10000) count = 0; if(count == 1) { PINS_DRV_SetPins(PTE,(1<<16u)...
void delay_test(int count) { while(count > 0) count--; } void spi_test() { uint8_t masterDataSend[3]; uint8_t masterDataReceive[3]; int count = 0; int flag = 0; while(1) { count++; if(count > 10000) count = 0; if(count == 1) { PINS_DRV_SetPins(PTE,(1<<16u)...
LPSPI_DRV_MasterTransfer(INST_LPSPI_1, master_buffer.tx, master_buffer.rx, 5); delayCycles(100); LPSPI_SetTxCommandReg(LPSPI0, &txCmdCfgSet ); the picture is add delay,it's ok this picture is not add delay, after transfer 4 data,the PCS is negate. Is this because the FIFO siz...
EDMA_DRV_Init(&dmaController1_State, &dmaController1_InitConfig0, edmaChnStateArray, edmaChnConfigArray, EDMA_CONFIGURED_CHANNELS_COUNT); If you have problems on receiving side for master device please set SAMPLE bit from CFGR1. This issue will be fixed on our next release. Best regards, Ra...